1. Field of Invention
This invention is related to a method of memory testing, and more particularly to a method for testing a random access memory (RAM) of an embedded system.
2. Description of Related Art
In view of the size of semiconductor manufacturing process evolves small and the level of the IC design industry advances, the IC product undoubtedly becomes complicated and delicate accordingly. Consequently, the IC product with higher reliability, better quality, lower cost and faster product launching is expected urgently by the buyer markets.
Due to the small size of semiconductor manufacturing process, the potential defects on the embedded memory are getting obvious frequently and these defects are especially easy to affect the effectiveness of the embedded memory. On the other hand, due to the advanced level of the IC design industry, Read-Only Memory (ROM), Random Access Memory (RAM) and Electrically Erasable Programmable Read-Only memory (EEPROM) are expected to frequently implement in the related industry.
For venders, the prior memory testing method mostly is RAM Stress Test (RST) method, in which the RST method tests endurance of the RAM by looping the program therein, whether a chipset is in malfunction or not.
However, the RST method merely provides tests of address lines and jumps of the RAM, hence the RST method fails to test the RAM completely and effectively and thus wastes much time in the duration of testing. Therefore, it is crucial for the entire industry to develop a new method for memory testing to improve the drawbacks discussed above and cut down the time for doing so.